Multiprocessor systems employ two or more computer processors that can communicate with each other, such as over a bus or a general interconnect network. In such systems, each processor may have its own memory cache (or cache store) that is separate from the main system memory that the individual processors can access. Cache memory connected to each processor of the computer system can often enable faster access to data than if accessed from the main system memory. Caches are useful because they tend to reduce latency associated with accessing data on cache hits, and they work to reduce the number of requests to system memory. In particular, a write-back cache enables a processor to write changes to data in the cache without simultaneously updating the contents of memory. Modified data can be written back to memory at a later time.
Coherency protocols have been developed to ensure that whenever a processor reads or writes to a memory location it receives the correct or true data. Additionally, coherency protocols help ensure that the system state remains deterministic by providing rules to enable only one processor to modify any part of the data at any one time. If proper coherency protocols are not implemented, however, inconsistent copies of data can be generated.
Multi-processor systems are also designed to assure memory consistency associated with memory reference operation ordering. Sequential memory consistency models require the memory reference operations of a process to appear to the rest of the system to execute in program order, even though much of the execution of the program can occur in parallel. The sequential consistency model imposes severe restrictions on the outstanding accesses that a process may have and effectively prohibits many hardware optimizations that could increase performance. A relaxed consistency model attempts to relax the constraints on the allowable event orderings, while still providing a reasonable programming model for the programmer. In a relaxed constancy model, an order is imposed between selected sets of memory reference operations, while other operations are considered unordered. One or more memory barrier or fences instructions are used to indicate the required order. However, no order is required between reference instructions that are not separated by a memory barrier or fence.